1. Field of the Invention
The present invention relates to a semiconductor device that includes an impedance adjustment unit.
2. Description of Related Art
As a data transfer speed between semiconductor devices increases, impedance of an output circuit is needed to become more accurate.
In particular, some DRAMS, which are one type of semiconductor memory, are so formed as to be able to change the impedance of an output circuit thereof at the time of data outputting in accordance with the impedance of a data bus connected to the DRAMs.
For example, Japanese Patent Application Laid-Open No. 2006-203405 shows a semiconductor device including an impedance adjustment unit that is designed to adjust the impedance of an output circuit. More specifically, the output circuit includes a plurality of unit buffer circuits; an impedance adjustment unit provided in common to the unit buffer circuits to adjust the impedances of the unit buffer circuits in common to a desired impedance. By changing the number of unit buffer circuits that are activated at the time of data outputting, the output circuit drives an output terminal with a required impedance.
The impedance adjustment unit uses a replica circuit corresponding to one unit buffer circuit to adjust the impedances of the unit buffer circuits in common. Meanwhile, the output circuit uses one or more unit buffer circuits to drive the output terminal. In this manner, if the output circuit uses two or more unit buffer circuits to drive the output terminal, the number of the unit buffer circuits that actually drive the output terminal is not reflected in the impedance adjustment unit. In the output circuit, according to the number of the unit buffer circuits activated, the voltage drop (and voltage rise) between a power supply line and a unit buffer circuit varies. Therefore, in the impedance adjustment process of Japanese Patent Application Laid-Open No. 2006-203405, there is concern that the impedance of the output circuit could deviate from the required impedance.